Hardware Implementation of Aes Encryption and Decryption for Low Area & Power Consumption

An AES algorithm is implemented on FPGA platform to improve the safety of data in transmission. AES algorithms can be implemented on FPGA in order to speed data processing and reduce time for key generating. We achieve higher performance by maintaining standard speed and reliability with low area and power. The 128 bit AES algorithm is implements on a FPGA using VHDL language with help of Xilinx tool. Keywords— Advanced Encryption Standard (AES), Field-Programmable Gate Array (FPGA), VHSIC Hardware Description Language (VHDL) --------------------------------------------------------------------***------------------------------------------------------------------